Self-aligned formation of the trench bottom shielding region in 4H-SiC trench gate MOSFET

To suppress the electric field in the gate oxide in a trench gate MOSFET (UMOSFET) with small cell pitch, we developed a technique to form the p+ region using self-aligned ion implantation under the gate trench. To prevent Al+ injection into the trench sidewalls, conditions of thin oxide layer deposition and Al+ implantation were optimized by process simulation. The resulting SiC trench MOS capacitors exhibited long-term reliability, with no degradation in lifetime by the p+ shielding region, and a specific on-resistance of 9.4 mΩ cm2 with a blocking voltage of 3800 V was achieved in the UMOSFET.