Old Web
English
Sign In
Acemap
>
Paper
>
High Density Copper Bump Technology Integrated With Wafer Level Package
High Density Copper Bump Technology Integrated With Wafer Level Package
2008
X. Zeng
Patty Chang-Chien
Chi Cheung
Gershon Akerling
Rosie Johnson
T. Chung
Kelly Hennig
Keywords:
Chip-scale package
Electronic engineering
Wafer
Thermal copper pillar bump
Copper
Wafer backgrinding
Embedded Wafer Level Ball Grid Array
Materials science
Optoelectronics
high density
Correction
Source
Cite
Save
Machine Reading By IdeaReader
0
References
2
Citations
NaN
KQI
[]