1.5 watt 622/155 Mbps single chip for full ATM-SDH/SONET physical layer in 0.5 /spl mu/m BiCMOS 3.3 V

A 622 Mbps single chip implementing the full ATM-SDH/SONET physical layer is presented. A low power chip architecture was developed concurrently with a power-adaptive ECL library resulting in a component with 1.5 W dissipation. Special precautions were taken in the analog blocks to reduce jitter; an 18 ps jitter was measured on the serial line. The die integrates 1M MOS and 8K bipolar transistors. Practical solutions to mix 1.2 GHz low jitter PLLs with digital blocks are reported. A reuse methodology was adopted, implying the creation of a VHDL reusable block library.