Ultrafast MRAM strategies for cache applications and beyond

In the ongoing Big Data revolution, the semiconductor industry faces major issues associated to the energy cost and time delay of transferring data between the processor cores and the multiple levels of memory. Since the advent of the MOS transistor, the performance of microelectronic circuits has followed Moore's law, stating that their speed and density would double every 18 months. Today, this trend tends to get out of breath: the continuously decreasing size of devices and increasing operation frequency lead to critical power consumption and heating issues. While the microprocessor unit is running in the GHz range, the main external memory (DRAM) is very slow. To speed up operations, cache memories, mostly composed of SRAM (Static Random Access Memory), are inserted between the processor and DRAM to fill this so-called “memory gap”. SRAMs are very fast but have a large footprint, hence a large silicon cost, which limits the amount of on-chip memory that can be practically embedded on-chip. Furthermore, SRAM are volatile which means that they require to be constantly powered and thus consume energy to retain information. With the downscaling of SRAM, this has today become a major issue [1] as the CMOS transistor current leakage has led to a large increase in the static (e.g. standby) power consumption. Moreover, the sensitivity to process and environmental variation reduces the static noise margin of SRAM, limiting their downscaling. Finally, the growing number of access to caches has also led to a large rise in dynamic power consumption. As multicore processors cannot afford keeping more than a very small fraction of all cores active at any given moment, their performances are limited and their scaling is hitting a power wall. As pointed by the ITRS, one of the best solutions to stop this trend is the modification of the memory hierarchy by the integration of nonvolatility (NV) as a new feature of memory caches, which would immediately minimize static power as well as paving the way towards normally-off/instant-on computing. The development of an electrically addressable nonvolatile (e.g. zero-leakage) memory combining processor speed (Ghz), infinite endurance and a higher-than-SRAM density is a crucial step towards higher performance and more energy efficient computing platforms.