Impedance matching method for jitter reduction of 28Gbps retimer

We developed a long channel backplane 28 Gbps transmission technology for next-generation high-speed I/O applications. To achieve long-channel backplane traces at 28 Gbps, main jitter sources such as ISI, crosstalk, power supply noise, and circuit origin including random jitter need to be drastically reduced. Among these, ISI is the largest jitter source. It is important to not only compensate for loss of channel but also reduce reflections due to impedance mismatch. Therefore, we proposed a low-jitter implementation technology for a package (PKG) and a print circuit board (PCB). This technique is a method to buffer the impedance mismatch by the impedance drop of a solder ball at high-speed transmission. By using the proposed technique, the ISI jitter can reduce 1 ps and EYE opening margin can be made larger than 0.04 UI.