Old Web
English
Sign In
Acemap
>
Paper
>
A-2-18 FPGA Implementation of a Discrete HC-ID Neural Network
A-2-18 FPGA Implementation of a Discrete HC-ID Neural Network
2014
Kosuke Matsui
Yoshihiro Hayakawa
Shigeo Sato
Koji Nakajima
Keywords:
Field-programmable gate array
Time delay neural network
Real-time computing
Artificial neural network
Computer science
Computer hardware
Correction
Source
Cite
Save
Machine Reading By IdeaReader
0
References
0
Citations
NaN
KQI
[]