The Effect of Process Parameters on Electrical Properties of High Density Through-Si Vias

This paper describes the process of copper through-Si via (TSV), 3 μm large and 15 μm deep, developed for tri-dimensional integrated circuits (3D 1C). The static resistance of this TSV was measured using a Kelvin structure and is 120±25 mΩ. A yield of about 95% was obtained on via chains made with 3200 TSVs per chain. An optimization of the TSV profile was also proposed by modifying the silicon etching process and by using SACVD deposition with 70% of step coverage to replace PECVD SiO film.