Multi-Level Integration of a Patternable Low-K Material in Advanced Cu BEOL

In this paper, we report, for the first time, on a simple, low-cost, novel way to form dual-damascene copper (Cu) on-chip interconnect or Back-End-Of-the-Line (BEOL) structures using a patternable low dielectric constant (low-κ) dielectric material concept. A patternable low-κ dielectric material combines the functions of a traditional resist and a dielectric material into one single material. It acts as a traditional resist during patterning and is subsequently converted to a low-κ dielectric material during a post-patterning curing process. No sacrificial materials (separate resists or hardmasks) and their related deposition, pattern transfer (etch) and removal (strip) are required to form dual-damascene BEOL patterns. We have developed a 248 nm patternable low-κ material with electrical and mechanical properties similar to those of a conventional plasma enhanced chemical vapor deposition (PE CVD) deposited low-κ material. This κ=2.7 patternable low-κ material is based on the industry standard SiCOH-based (silsesquioxane polymer) material platform and is compatible with 248 nm optical lithography. We have also successfully demonstrated single- and dual-damascene integration of the novel patternable low-κ dielectric material into advanced Cu BEOL. Furthermore, we have demonstrated multi-level integration of this patternable low-κ material at 45 nm node Cu BEOL fatwire levels with very high electrical yields using the current BEOL manufacturing infrastructure. Therefore, the patternable low-κ material concept is a promising technology for highly efficient, low-cost semiconductor BEOL manufacturing.