An Adiabatic Content-Addressable Memory Based on Dual Threshold Leakage Reduction Technique

This paper presents a CAM (Content-Addressable Memory) using dual threshold leakage reduction technique. A 16(16 CAM is demonstrated using the proposed dual threshold technique based on CPAL (complementary pass-transistor adiabatic logic) circuits. All circuits are verified using HSPICE in different temperature, high-threshold voltage, and active ratios in 45nm technology. BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses of the CPAL CAM using dual threshold leakage reduction technique are obviously reduced both in work mode and idle mode compared with basic CPAL one using single threshold transistors.