High performance low Vcc operation by hiding repair information access latency

Bit errors in SRAM are one of the most critical problems in reducing supply voltage. Existing methods to address this problem share a common issue of additional latency in SRAM access for error correction or data repair. The additional latency increases clock period thereby losing opportunities of further reduction in supply voltage. In this paper, we propose an architectural retiming to hide the additional latency for data repair. It reduces clock period (typically determined by the memory access stage at low supply voltage) by moving the function of data repair information access from the memory access stage to an earlier pipe stage. Our case study with an existing CPU core design shows that the proposed method offers up to 42% higher operating frequency at 0.6V.