THE INDEPENDENT EVALUATION OF THE SCIENCE TEACHERS INITIATIVE (CASCITI)

A bus bridge circuit having at least one register to store address ranges to enable or disable prefetch in upstream memory read transactions or upstream write transaction buffering/posting data to specific devices. The use of address ranges allows the present invention to provide selectable control of prefetch for upstream memory read transaction flow. This feature allows the continued use of read prefetch for targets that allow upstream read prefetch while disabling upstream read prefetch for targets that do not allow upstream read prefetch. Additionally, the use of the address range allows upstream memory write transaction flow without utilizing data buffering or posting for specific targets. This feature provides immediate delivery of upstream data to selected targets by selectively disabling buffering/posting of upstream memory write commands as performed by a FIFO buffer. Thus providing immediate delivery of upstream data to selected targets while buffering/posting upstream memory write commands for other targets.