Multi-Layer Ceramic Capacitor and Printed Circuit Board embedding the same

The present invention relates to a laminated ceramic capacitor and a printed circuit board having the same, capable of minimizing deviation in thickness of electrodes and laminated ceramic. A laminated ceramic capacitor according to an embodiment of the present invention includes laminated ceramic and outer electrodes formed on both sides of the laminated ceramic, wherein (Tmax - Tmin) is 10 μm or less and (CTmax - CTmin) is 20 μm or less (wherein Tmax is the maximum thickness of the outer electrode in a via processing region, Tmin is the minimum thickness of the outer electrode in the via processing region, CTmax is the maximum thickness of the laminated ceramic capacitor in the via processing region, and CTmin is the minimum thickness of the laminated ceramic capacitor in the via processing region).