A new vertical MOSFET "Vertical Logic Circuit (VLC) MOSFET" suppressing asymmetric characteristics and realizing an ultra compact and robust logic circuit

Recent studies focused on the vertical MOSFET's have brought out their performance merits, such as 1) the transistor area reduction for the circuit design, 2) no threshold increase by the back-bias effect, 3) the suppression of the short channel effect, 4) the sub-threshold swing decrease, and 5) the increase in the driving current density [1]-[4]. However, due to the device structure of the typical vertical MOSFET's, the top and bottom contacts for the source or drain have different resistances because there is a diffused silicon wiring area in the bottom. Thereby, it has the asymmetric current characteristics [5] between the top and bottom nodes. So far, the impacts on the practical circuit performance with the vertical MOSFET's have not been investigated in details. This paper is devoted to examining the asymmetric characteristics of the conventional vertical MOSFET, proposing a new vertical MOSFET which can suppress the asymmetric characteristics, and validating its impact on an ultra compact and robust logic circuit.