ESD characterization of Grounded-Gate NMOS with 0.35µm / 18V technology employing Transmission Line Pulser (TLP) test

We have investigated ESD (Electro-Static Discharge) properties of GGNMOS (Grounded Gate NMOS), which is fabricated via 0.35µm / 18V logic technology, employing TLP (Transmission Line Pulser) test. Measurement results show that 18V GGNMOS exhibits the snap-back characteristics, which result in the high ESD immunity level of 9.5mA/µm in the single finger type and 5mA/µm in the multi-finger type. Good linear dependence on the width scaling is achieved both in the single finger type and in the multi-finger type GGNMOS. We have also simulated to investigate the ESD failure mechanism and effects of layout design parameters on the ESD immunity level of 18V GGNMOS. Simulation results show that the ESD failure mechanism in 18V GGNMOS is the low-temperature second breakdown induced by Kirk effect and the ESD immunity level is increased as XO and DCGS are increased. Experimental results show that 18V GGNMOS is robust to ESD stress, while DENMOS (Drain Extended NMOS) and LDMOS (Lateral double Diffused MOS) are vulnerable to ESD stress [2,3].