Qualification method for a 1MGy-tolerant front-end chip designed in 65nm CMOS for the read-out of remotely operated sensors and actuators during maintenance in ITER

Abstract This paper describes the radiation qualification procedure for a 1 MGy-tolerant Application Specific Integrated Circuit (ASIC) developed in 65 nm CMOS technology. The chip is intended for the read-out of electrical signals of sensors and actuators during maintenance in ITER. First the general working principle of the ASIC is shown. The developed IC allows to read-out, condition and digitize multiple low bandwidth (