Channel timing error analysis for DDR2 memory systems

This paper presents an accurate simulation method to extract channel timing errors for DDR2 memory systems. The paper first describes various timing constraints related with DDR2 channels and elaborates on the crucial design issues associated with these timing constraints. The overall optimization of DDR2 timing constraints is quite challenging since they are coupled with common timing components such as clock jitter, strobe delay, etc. Then, this paper proposes an edge-based timing extraction approach to calculate key channel timing components instead of the traditional timing analysis based on an eye diagram. The edge-based approach results in accurate timing values which closely resemble the actual channel timings seen from a receiving device. The proper source and target models are also proposed in order to extract the channel timing error from the overall system timing error which includes the device timing error. A DDR2 system with two 667Mbps DDR2 devices is used to illustrate the proposed methodology.