A Self-Aligned Gate-Last Process Applied to All-III–V CMOS on Si

Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are co-processed and co-integrated using a gate-last process, enabling short gate-lengths (L g = 40 nm) and allowing selective digital etching of the channel. Two different common gate-stacks, including various pre-treatments, were compared and evaluated. The process was optimized to achieve high n-type performance while demonstrating p-type operation. The best n-type device is scaled down to 12-nm diameter and has a peak transconductance of $2.6\ \text{mS/}\mu \text{m}$ combined with a low R on of $317~\Omega \cdot \mu \text{m}$ , while the p-type exhibits $74~\mu \text{S}/\mu \text{m}$ . In spite of increased complexity due to co-integration, our n-type InAs transistors demonstrate increased drive current, $1.8\ \text{mA/}\mu \text{m}$ , compared with earlier publications.