Numerical Analysis of Packaging-Induced Failures in Cu/Low-k Interconnects

With decreasing feature sizes for every technology node, multi-level metallization schemes that employ copper interconnects and low-k dielectrics are required to achieve the requisite circuit performance. Here, the effects of the mechanical stresses originating from the packaging process on Cu/Low-k interconnects are assessed. The impact of package defects on interconnect reliability is also analyzed. It is seen that the package reliability varies with underfill mechanical properties. The packaging process introduces global level stresses that propagate to the local, i.e. interconnect, level. Moreover, the package defects also have an adverse impact on the mechanical stresses in the metallization structure. The package defects alter the mechanical stresses in the metal lines and affect the reliability. The complex interaction between packaging process induced stresses, package level defects and mechanical properties of various materials is analyzed in order to create robust interconnect designs.