Interconnection Technology Innovations in 2.5D Integrated Electronic Systems

Vertical interconnections, called through‐silicon vias (TSVs), play a key role in enabling silicon interposer‐based 2.5D integration (and 3D chip stacking). HIST 2.5D integration forms concatenated ICs using heterogeneous IP blocks (from multiple foundries) enabled by a combination of 2.5D integration and face‐to‐face 3D integration technologies. This chapter first discusses silicon interposer TSV technologies with improved thermomechanical and high frequency electrical properties. To reduce TSV stresses and electrical losses, polymer‐enhanced TSVs are used. The polymer‐enhanced TSVs described here include polymer‐clad TSVs (which feature thick polymer liners) and polymer‐embedded vias (which feature an array of copper vias formed within a polymer well). Then, the chapter describes the HIST approach in more detail and share key features, by proposing an alternate TSV‐less heterogeneous integration technology. For forming concatenated ICs using heterogeneous IP blocks, a combination of solder bumps and mechanically elastic and fine‐pitch CMIs is utilized to robustly assemble the ICs.