Synchronous SFQ address encoder for superconductor detector arrays

With the advances in superconductor detectors and single flux quantum (SFQ) logic circuits, megapixel imagers have become possible. Various detectors such as superconducting stripline detectors (SSLD), kinetic inductance detectors, nanowire single-photon detectors have quite matured in terms of speed and performance. However, scaling of the read-out electronics is still a challenge. We propose an SFQ based synchronous address encoder to read-out the response of an SSLD array. The encoder circuit provides two sets of outputs at each clock period: one is the time-division multiplexed, serial data output, and the other is the synchronized address output associated with the time-multiplexed data. Thus, the number of connections to the room temperature is substantially reduced. We experimentally demonstrate a 2-bit encoder. Then, we present the scalability of the circuit to larger arrays and show the simulation results of a 4-bit encoder, which is suitable to read-out a 16 × 16 detector array.