Performance comparison review of 8–3 compressor on FPGA

Compressors are commonly utilized in multipliers for reducing partial products in a parallel manner. In this paper 7–3, 7–4, 8–3, 8–4, 9–3, and 9–4 compressors designed with adder circuits or multiplexer circuits were implemented in Altera EP2C70F896 FPGA and their performance compared in terms of number of logic gates used, cell area and power delay product (PDP) for an optimum recommendation for the implementation of 8–3 compressor design in FPGA.