Reducing Power Consumption in Asynchronous MTNCL Circuits through Selective Sleep

The conventional synchronous approach for designing digital integrated circuits (ICs) requires large clock trees to effectively coordinate the operation of the circuit. These clock trees consume a substantial amount of power. Multi-Threshold NULL Convention Logic (MTNCL) is an ultra-low power quasi-delay-insensitive (QDI) asynchronous circuit design paradigm utilizing local handshaking signals instead of a global clock for harmonized circuit communication. Traditional MTNCL circuits require full sleep trees, i.e., the sleep signal is connected to every logic gate to generate NULL waves during operation, which limit their power reduction compared to the synchronous counterparts. This paper presents a technique named Selective Sleep to reduce the size of sleep trees in MTNCL circuits for power saving while maintaining proper asynchronous handshaking. Transistor-level schematic simulations in the TSMC 65nm process show that Selective Sleep reduces the active energy and leakage power in MTNCL circuits with minimal throughput overhead. These results indicate that Selective Sleep is well-suited for applications with strict power constraints and long idle time such as the Internet of Things (IoT).