A 6-ns 4-mb Cmos Sram With Offset-voltage-insensitive Current Sense Amplifiers

A 4-Mb CMOS SRAM with 3.84 μm 2 TFT load cells is fabricated using 0.25-μm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells