Improvement in threshold-voltage uniformity in submicrometer GaAs MESFET's using an implanted p layer

A significant improvement in threshold-voltage uniformity for submicrometer gate GaAs MESFET's fabricated by direct Si implan, tation was observed using an optimized p-buried layer on conventional undoped LEC-grown substrates. Using an optimized Be-implantation scheme, we have achieved standard deviations of the threshold voltage as low as 7.6 mV from 13 × 13 FET arrays and only 16.8 mV across a 3-in wafer for FET's with a gate length of 0.6 µm. This is a very promising result for extending the GaAs MESFET IC technology into VLSI circuit complexity.