Complementary-Symmetry/Metal Oxide Semiconductor (CMOS) Circuit Hardening. Volume I. Silicon-on-Sapphire (SOS) CMOS Circuit Fabrication and Characterization.

Abstract : This report summarizes the results of Phase I of a three-phase program to develop and verify hardening techniques in Complementary-Symmetry/Metal Oxide Semiconductor (CMOS) Large Scale Integrated (LSI) circuits fabricated with Silicon-on-Sapphire (SOS) technology. The Phase I study examined, experimentally, the effects of threshold voltage shifts on the electrical performance and transient radiation response in basic CMOS/SOS circuits. Simple CMOS/SOS test circuits, including an inverter, a 2-input NAND gate and a 2-input NOR gate, were fabricated with a 5 x 5-matrix of p-channel and n-channel threshold voltages. Results of electrical measurements are reported which show the variations that can be expected in electrical operation of these circuits, arising from the matrix of threshold voltage combinations. These threshold voltages can result from exposure to ionizing radiation or instability in the gate insulator material. Results of transient radiation measurements are reported which show the transient failure levels that can be expected in CMOS/SOS circuits and the significance of different threshold voltage combinations and sapphire photoresistive effects on the transient radiation hardness. (Author)