Formal Verification of a Reconfigurable Microprocessor

The increasing acceptance of reconfigurable logic in form of FPGAs or CPLDs has caused new research activities in the field of processor architecture, the reconfigurable processors. The basic idea consists in combining the flexibility of reconfigurable logic with the transparent and well-known instruction set programming model. In this way critical parts of the application can be implemented directly in hardware. It has been shown that reconfigurable microprocessors are able either to achieve speed-ups or to improve the cost/performance ratio for a broad range of applications [1].