Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing

This paper presents an all-digital bi-directional gated Vernier delay line (BDGVDL) time integrator for time-mode signal processing. The time integrator features a high resolution and the suppression of even-order harmonic. Design considerations of per-stage-delay mismatch and catch detection latency are examined and design guidelines on choosing the delay of catch-detect DFFs are obtained. The simulation results of the time integrator designed in a TSMC 130 nm 1.2 V CMOS show the time integrator provides 22 dB gain, 50 ps time resolution, and consumes 1.76 mW at 40 MS/s. The dynamic range of the time integrator is lower-bound by the metastability window of catch-detect DFFs and upper-bound by the number of the stages of the BDGVDL.