Dynamic heterogeneity with fusion integrated reconfigurable execution (fire)

As predicted by the Moore's law, the number of transistors per chip and the core frequencies continue to grow. However, the basic technological issues such as heat dissipation, leakage currents, and the signal run-times make it extremely challenging to reap benefits of the transistor count using existing architectural techniques. The microprocessor architectural research community is at a crossroad of design decisions. Multi-core processors comprised of several low power, low frequency cores were proposed as a means of utilizing higher density chips. A challenge remains of how to keep a large number of symmetric cores busy due to the architectural design constraints such as memory interface bottlenecks and instruction scheduling logic complexity. The potential throughput of low frequency (many) in-order cores may also not be realized due to scheduler complexity an inherently limited instruction level parallelism in single threaded applications. A vast body of contemporary research shows that in order to effectively utilize billions of on-chip transistor gates and sustain high throughput, the existing design philosophy needs to adopt an optimal combination of compute resource scheduling granularity and heterogeneity. Reconfigurability of compute resources is an effective way to dynamically attain heterogeneity of cores suitable to match a variety of workloads. This dissertation presents a model for reconfigurable processor design space exploration. Analytical research conducted to determine an effective reconfiguration strategy for different types of workloads are discussed. A dynamically reconfigurable spatially parallel datapath extension to a conventional out-of-order superscalar processor is designed. A novel architectural approach that leverages a limited dataflow based reconfigurable datapath called Fusion Integrated Reconfigurable Execution (FIRE) that executes instruction chains grouped as macro-operations (MOPs) is presented. The hardware mechanisms for dynamically exposing the program dataflow and adaptively reconfiguring a spatial datapath are included. The FIRE design is transparent to the existing microarchitectural techniques and compatible with legacy compiled programs.