A Compact, Voltage-Mode Type-I PLL With Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter

Despite their inherent stability, area-efficient loop filters, and insensitivity to phase-frequency detector nonlinearity and dead-zone, type-I phase-locked loops (PLLs) are used infrequently because of two major limitations—limited lock-range and large reference spurs. This paper introduces a type-I PLL that takes advantage of the inherent benefits of the architecture, while tackling its limitations by means of gain boosting in the forward path for lock-range improvement and synchronous peak tracking of the voltage-controlled oscillator control voltage for reference spur reduction. Sampling in the loop filter changes the loop dynamics, and methods to accurately predict the closed-loop response, starting from state-space equations, are provided. A digital-friendly, voltage-mode topology is proposed that does not need charge pumps or opamps. A prototype 2.2–2.8-GHz PLL occupies a core area of 0.12 mm 2 in 0.13- $\mu \text{m}$ CMOS and achieves −103.4 dBc/Hz in-band phase noise, −65-dBc reference spur, and 2.5- $\mu \text{s}$ worst-case lock-time while consuming 6.8 mW from a 1.2-V supply.