Performance-Power Management Aware State-of – the-Art 5nm FinFET Design(5LPE) with Dual CPP from Mobile to HPC Application

In this paper, we demonstrate state of the art 5nm technology (5LPE) having co-optimization process for Dual CPP (Critical Poly-Pitch) technology to maximize Product Power-Performance-Area by separating both high speed and low power blocks. As a result, 5LPE successfully has 10% speed gain or 20% power gain and 0.75x logic area over our previous 7nm technology [1] with more advanced FinFET technology having EUV process and design optimization.