FPGA Implementation of Wave Digital Filters with Multiple exp-based Nonlinearities

In this paper, an FPGA implementation of a Diode Clipper circuit as an application of Wave Digital Filters with multiple exp-based nonlinearities is presented. Therefore, an efficient look-up table design in combination with an iterative approach, namely Newtons’s and Halley’s method is proposed for real-time evaluation of the Lambert function. A sequential and a concurrent version of the circuit were implemented, for each of which FPGA resource utilization and a rule for latency depending on the iteration steps required were determined. It is shown that although Halley’s method generally converges faster, the overall latency is the same for Newton’s method while achieving same accuracy and being more resource-saving.