10T Sram cell designusing single ended decoupled read bit line

Read stability and read speed are the most likely problems encountered in the cells of the SRAM. The access transistors used to access the basic latch takes extra time to read the cell data during the read operation, and more over there exists a possibility of external noise corrupting the cell data. The problem of consumption of extra read time and possibility of noise corrupting the cell data can be circumvented by making use of 10T SRAM cell, modified with single ended decoupled read bit line, providing advantage of speed and noise margin. The conventional 6T SRAM cell is equipped with word line for both read and write processes, but the proposed 10T SRAM cell uses a different read enable line to read the stored bit. This allows the memory element to remain isolated from the external disturbance, additionally the extra time required to activate the access transistors is not required as the read operation in this cell does not require it. The design of read behaviour is analyzed using tanner tool 180nm technology and compared with the reported basic 6T structure.