20-Gb/s 5- $\text{V}_{\mathrm{PP}}$ and 25-Gb/s 3.8- $\text{V}_{\mathrm{PP}}$ Area-Efficient Modulator Drivers in 65-nm CMOS

This brief presents two area-efficient drivers for a 50- $\Omega$ terminated optical modulator. Driver 1 adopts a double cascode with dynamic biasing that enables sufficient high-speed operation owing to the high transition frequency of the thin-oxide transistor. Therefore, it does not require area-consuming additional peaking inductors. A custom-designed shared inductor is used in Driver 2 for bandwidth enhancement with a small area penalty; the required total inductance is only 13.3% of the conventional shunt peaking case. The prototypes are fabricated in a 65-nm complementary metal–oxide–semiconductor process. Electrical measurement results show that Driver 1 exhibits a differential output swing of 5 $\text{V}_{\mathrm{PP}}$ , a data rate of 20 Gb/s, and a power consumption of 534 mW. The measured performance of Driver 2 is 3.8 $\text{V}_{\mathrm{PP}}$ and 348 mW at 25 Gb/s. The active areas of the proposed modulator drivers are only 0.068 mm 2 and 0.038 mm 2 .