EMBEDDED EPICS ON ITRON/SH4-BASED CONTROLLERS

Many Japanese Ethernet-based controllers being used in accelerator control systems adopt ITRON for their real-time kernels. Since those controllers have enough CPU power and memory capacities, IOC core program (iocCore) can run directly on them to realize "Embedded EPICS". The only viable option to achieve Embedded EPICS on various different controller types is to utilize BSPs available on the market as they are, since developing BSPs every time we support a new target is too expensive. Based on preceding investigation on technical feasibility, we have ported iocCore onto a target running ITRON on an SH4 CPU [1]. As a result, a fully functional IOC, which has all of the IOC software components such as Channel Access (CA) server and run-time database, was realized on the ITRON/SH4-based target. In addition, we carried out a jitter measurement to evaluate the real-time performance of the ITRON-based IOC. The result showed that, after fixing a problematic code of EPICS for time difference calculation, the ITRON-based IOC has the real-time responsiveness as expected.