Design of a 640 Gbps Two-Stage Switch Fabric for Satellite on-board Switches

Due to the limitation of hardware resources and high reliability requirements for satellite-borne switching equipments and the demand for the increasing network bandwidth, a new type of two-stage satellite on-board switch fabric is presented in this paper. The fully connected structure is composed of eight input modules and eight output modules. And each module has four shared-buffer memories, which guarantee the premise of high-throughput. Compared with the traditional three-stage CLOS switch fabric, central modules are not used in this design. And compared with the complicated inter-stage scheduling algorithm, this paper uses an improved WRR algorithm which supports multi-priority variable-length packets scheduling. This design reduces the consumption of hardware resources and meets the design requirements of satellite-borne switches. In addition, we used the Xilinx FPGA to implement this $32\times32$ two-stage switch fabric, and used ModelSim 10.6d to simulate and analyze the entire design. The simulation results show that the peak throughput of this structure can reach 640 Gbps when the system clock frequency is 200 MHz.