Dopant-Segregation Technique for Leakage Reduction and Performance Improvement in Trigate Transistors Without Raised Source/Drain Epitaxy

A dopant-segregation technique for junction engineering has been demonstrated on trigate transistors using a process flow that does not include raised source/drain epitaxy. It is shown that the dopant-segregation technique reduces the OFF-state leakage current and improves the ON-state performance for NFET devices when compared with control devices built using conventional junction engineering. The dopant-segregation process has no observable impact on PFET device performance.