A CMOS analog frontend for a passive UHF RFID tag

The paper discusses the design of the analog frontend of a passive UHF RFID tag, compatible with ISO/IEC 18000-6b standard. An efficient ESD-protected power retrieving circuit, based on the antenna features, a rectifier bridge and a charge pump, is introduced, as well as an auto-calibrated clock generator. The chip, implemented in a 0.18?m digital CMOS technology, does not need any post-fabrication trimming or external component besides the antenna; according to simulations, a correct communication is achieved at a distance of several meters between reader and tag.