Ultrathin EOT (0.67 nm) High-k Dielectric on Ge MOSFET Using Y Doped ZrO 2 With Record-Low Leakage Current

An advanced gate stack of Y-doped ZrO 2 high-k dielectric is demonstrated for Ge MOSFETs. ZrO 2 is implemented due to its high-permittivity (high-k) value, and additional Y is doped into the ZrO 2 to enhance interfacial properties. The gate stack of ZrO 2 with 2~4% Y doping shows improved electrical properties, achieving an EOT of 0.67 nm, a low interface trap density ( $\text{D}_{\textsf {it}}$ ) of $\textsf {1.2}\,\,\times \,\,\textsf {10}^{\textsf {12}}$ eV −1 cm −2 , a record-low gate leakage current of $\textsf {1.14}\,\,\times \,\,\textsf {10}^{-\textsf {7}}$ A/cm 2 at −1V, and peak mobility of $\textsf {68 cm}^{\textsf {2}}/\textsf {V}\cdot \textsf {s}$ . The proposed gate stack would enhance transistor speed and save power consumption of Ge MOSFETs.