An Efficient Network-on-Chip Yield Estimation Approach Based on Gibbs Sampling

A network-on-chip (NoC), a redundancy-rich and thus relatively robust system-chip, is still vulnerable to defects due to its large-scale integration. Thus, it is desirable to analyze the NoC yield in an early design phase. A Monte Carlo (MC) approach was proposed for the NoC yield analysis at the system level; however, it is inefficient due to the requirement of a large number of simulation runs. In this paper, we propose a Gibbs sampling approach, which can efficiently generate failed NoC instances as simulation samples, for yield estimation. This approach significantly reduces the number of required simulation runs for obtaining an accurate yield estimation. Implementation issues, such as initial sample selection, calculation of conditional distributions, and stop criterion, to customize Gibbs sampling for the NoC yield analysis are discussed. Potential optimization opportunities to further improve Gibbs sampling’s efficiency are also explored. Compared to the MC approach, our experimental results show that the proposed approach can reduce the simulation runtime by $ {5\times }$ – $ {100\times }$ for a high-yield NoC (a failure rate at $ {10^{-2} }$ – $ {10^{-5} }$ ), while achieving the same level of accuracy for yield estimation.