Double patterning using dual spin-on Si containing layers with multilayer hard mask process

A new technology called the double patterning (DP) process with ArF immersion lithography is one of the candidate fabrication technologies for 32 nm-node devices. Over the past few years, many studies have been conducted on techniques for the DP process. Among these technologies, we thought that the double Si hard mask (HM) process is the most applicable technology from the viewpoint of high technical applicability to 32 nm-node device fabrication. However, this process has a disadvantage in the cost performance compared with other DP technologies since these HMs are formed by the chemical vacuum deposition (CVD) method. In this paper, we studied the DP process using a dual spin-on Si containing layer without using the CVD method to improve process cost and process applicability. Perhydropolysilazane (PSZ) was used as one of the middle layers (MLs). PSZ changes to SiO 2 through the reaction with water by the catalytic action of amine in the baking step. Using PSZ and Si-BARC as MLs, we succeeded in making a fine pattern by this novel DP technique. In this paper, the issues and countermeasures of the double HM technique using spin-on Si containing layers will be reported.