Basic and advanced characterization techniques for nano-structures and devices

Welcome to a Fully-Depleted (FD) world! Full depletion is a universal attribute of advanced MOS devices such as planar SOI, semi-vertical FinFETs (on bulk or SOI), nanowire and junctionless transistors. The key point is that FD MOSFETs exhibit excellent electrostatic capability leading to far better scalability than in bulk CMOS. This tutorial is intended to participants familiar with ‘bulk’ technology who wish to gain additional expertise in the electrical characterization of FD devices. The goal is to offer a comprehensive view of the general strategy and recommend practical methods. The evaluation of SOI structures is hampered by the thinness of the body and the presence of multiple surrounding interfaces. Nano-size materials being FD, the recommended technique is the Pseudo-MOSFET which is routinely technique for SOI wafer evaluation. We will next see how to manipulate single-gate and multiple-gate MOSFETs in order to reveal, from their static and dynamic characteristics, key parameters: carrier mobility and lifetime, threshold voltage, series resistance, interface traps and oxide defects, self-heating, leakage currents, etc. More sophisticated techniques like split-CV, geometric magnetoresistance, low-temperature transport, charge pumping, transient currents, and noise spectroscopy will also be described. Finally, it will be shown that the floating-body and multi-channel coupling are complex mechanisms requiring special treatment: they alter the measurements but, in turn, they offer practical advantages.