Discrepancy Reduction Between the Topology of Dataflow Graph and the Topology of FPGA Structure

One of the main limiting factors in dataflow supercomputing is the discrepancy between the topology of a typical dataflow graph (produced by compiler) and the typical topology of FPGA structure (produced by manufacturer) onto which the execution graph has to be mapped. One possible school of thought is to study cases where infinitesimal changes in hardware domain may generate much more than infinitesimal impact in the benefit domain (speed/complexity/power/risks). The research analyzes the effects of one such infinitesimal add-on in the hardware domain (moving from two-input adders to three-input adders). Different compilation techniques, debugging and optimizing tools and methods, offered by “Maxeler Technologies Ltd.,” are presented and elaborated.