Emerging Standards at ~10 Gbps for Wireline Communications and Associated Integrated Circuit Design and Validation (An Invited Paper for CICC 2009)

We first review the signaling and jitter requirements for emerging high-speed wireline communication standards at ~10 Gbps, including CEI 11G, XLAUI/CAUI, XFI, and SFP+. We then present an FPGA transceiver architecture and subsystem/circuit blocks for clocking and timing generation, transmitter buffer, and receiver CDR and DFE, all designed and manufactured with 40-nm process node. Lastly, we present the signal/jitter transmitter output and receiver-tolerance measurement results at 10.3125 Gbps, with an ultra-low random jitter at ~550 fs. I. INTRODUCTION Semiconductor technology advancements largely follow Moore's Law in that the number of transistors in integrated circuits doubles roughly every two years. Moore's Law is facilitated by the feature size or process node shrinkage. Smaller features enable more functionality and integration, higher operation speed and logic density, and lower power consumption per logic function. As the device functionality and logic density increase, the I/O bandwidth must increase proportionally, which is achieved by increasing the data rate for each I/O lane. A higher data rate often is achieved through using advanced design methodologies and process technologies. The smaller feature size implies a smaller channel length for a transistor and shorter interconnects for a logic gate, resulting in faster switch time and shorter interconnect transport delay. 40 nm is the leading-edge process node used for some advanced, high-density, and high-performance devices, including microprocessors, FPGAs, and graphic processors. At the present, the data rates for most high-speed transceivers are in the range of 5-6 Gbps for communication and I/O standards. A few