FPGA HardCore single processor implementation of RT control applications

In recent years, field programmable gate array (FPGA) have proven themselves capable of handling a wide variety of tasks, from relatively simple electrical system control functions to more complex, algorithmic operations. According to the controller complexity, the FPGA design can be achieved by mixed Software/Hardware solutions. However, in many cases, the FPGA-based controller architectures require extensive real time (RT) testing before applying in real conditions. Thus, this paper will propose new approach to test controller design by implementing real time motor emulator linked to its controller drive in the same system on chip (SoC). The gain with using this new approach is the ability to push past the operational limits of a specific environment and to test fault conditions that would otherwise be damaging or dangerous for a real motor. The proposed work describes an FPGA HardCore single processing implementation of a RT motor control loop and then explores the viability and cost-performance of this FPGA design.