Effects of High Temperature Process Steps on Void Size Distributions in Passivated, Narrow Aluminum Lines

Narrow Al lines were passivated at 300°C and subsequently annealed at 400°C for an hour. The passivation layer was then removed and the lines analyzed for thermal stress induced voids. Effects of the multiple high temperature process steps necessary in chip manufacturing were simulated by repeated anneals. Renewed void nucleation occurred during cool-down from each anneal, leading to a systematic increase in void density. In contrast, the maximum void size did not increase with number of anneals while it did increase with aging time for a single anneal.