Performance of Submicron Silicon MOSFETs Fabricated by Edge-Defined Vertical-Etch Technique

This paper describes the performance of n-channel and p-channel submicrometer silicon MOS devices fabricated by edge-defined vertical etch techniques. Submicrometer MOS devices with gate length of 0.3 to 0.6 μm and gate oxide thickness of 8 to 16 nm have been fabricated with self-aligned, lightly doped source/drain extensions using a sidewall oxide spacer technology. Some of the devices have been fabricated with PtSi formed on the gate and source/drain to reduce series resistance. Mobility, linear and saturation gain, and drain saturation current have been examined as a function of gate length. Finally, ring oscillator performance for both n-channel and p-channel devices is discussed.