Metal-oxide-semiconductor field-effect transistor layout structure

Disclosed is a metal-oxide-semiconductor field-effect transistor layout structure, which employs a common drain area having a right cross-shaped pattern and at least two common drain areas having tartan design, and a mixed array having a right cross-shaped pattern common drain area and a right cross-shaped pattern common source electrode which are formed by a common source electrode area having a right cross-shaped pattern and at least two common source electrode areas having tartan design. The metal-oxide-semiconductor field-effect transistor layout structure can improve the assembly density of the conventional layout circuit and promote the width of the efficient information channel thereof, thereby realizing the objective of reducing the cost and operation with higher power.