fcCuBE technology: A pathway to advanced Si-node and fine pitch flip chip

fcCuBE™ technology by STATSChipPAC has gained significant momentum due to several benefits it offers, namely; Bump Pitch (BP) reduction capability with Cu-column interconnect, cost reduction as a results of substrate design rule relaxation associated with Bond-On-Lead (BOL) and Open Solder Resist (SR) design, and advanced FAB node compatibility due to significant reduction of stress on Extreme low-K (ELK) die-electric layers. Additionally it can result in further cost reduction for special case applications that can benefit from substrate layer count reduction [2], as well those cases that require conversion of wire bond die to flip chip design through the elimination of the costly RDL process that otherwise would be needed for such conversion [5]. With the benefits described above in terms of technology and cost, and the common trend of pitch reduction seen across devices in virtually all market segments including Networking, Mobile devices, Computing, and Consumer Electronics, the adoption of this technology is becoming more widespread. This paper illustrates the feasibility and extendibility of the fcCuBE technology to advanced Si-nodes (28N) and fine pitch applications using the conventional reflow process down to 80um Bump Pitch (BP) and adoption of ThermoCompression Bonding (TCB) process for sub-80um BP to cater to extremely small bump diameters and increased sensitivity to unit warpage and surface non-planarities. In defining the Cu column application space for advanced FAB nodes and fine pitch flip chip packages, a number of design configurations have been considered and qualified. One such configuration describes the development activity using a full functional 28nm Si with Cu column at 140um BP and BOL design where all reliability tests have successfully passed in side-by-side comparison to the Lead-Free (LF) solder bump design version with Solder-On-Pad (SOP). Integration of Cu column with BOL design is evaluated in 28nm Si node where the improved ILD (Inner Layer Dielectric) crack margin gained by BOL design is proven through reliability tests and multiple reflow (Hammer test) studies in side-by-side comparison to the LF solder bump version of the same 28nm TV. Process characterization on 80um BP Daisy Chain (DC) TV using the conventional reflow process is also demonstrated with successful reliability results to prove the process extendibility of fcCuBE with conventional reflow process. In parallel, process characterization of fcCuBE technology using thermo-compression bonding (TCB) process is also demonstrated using sub-80u BP DC TV, thus ensuring the compatibility of fcCuBE technology across the entire spectrum of fine pitch Flip chip applications.