System-level design space identification for Many-Core Vision Processors

Abstract The current main trends in the embedded systems area, the Cyber-Physical Systems (CPS) and the Internet-of-Things (IoT), are leveraging the development of complex, distributed, low-power, and high-performance embedded systems. An important feature needed in this new Era is the embedded intelligence enabling to locally process data and actuate over the environment, without the need of a remote central processing server. In this context, emerged the Smart Cameras: devices able to acquire images and apply sophisticated algorithms for different Image Processing and Computer Vision (IP/CV) applications. Both the technology convergence and the evolution of embedded systems to multi/many-core architectures allow envisioning future cameras as many-core systems able to efficiently explore the natural IP/CV parallelism to meet embedded application’s constraints, e.g. real-time, power consumption, silicon area, temperature management, fault tolerance, among others. In this work, we show the development of a Many-Core Vision Processor architecture, suitable for future Smart Cameras. In our design methodology, we analyze several aspects involved, from high-level application analysis down to fine-grained operations and physical aspects (e.g. geometry and spatial distribution). The main analysis is performed using a SystemC/TLM2.0 simulator specially developed for this project. Silicon Area, Power Consumption and Timing estimations are also provided as results of an early Design-Space Exploration (DSE). Using these results we propose a first complete architecture, which is implemented in an FPGA. Details about the hardware implementation are provided, as well as synthesis results. In comparison to other works, from the literature, the implemented architecture shows the potential of the project developed in this work.