Silicon Nanostructures Patterned on SOI by AFM Lithography

ABSTRACT The actual trends in microelectronics are the reduction of the dimensions and the search of new devices standing upon new phenomena as in the case of a Single Electron Transistor (SET) that is based on the Coulomb blockade. The nowadays limitation for device dimensions is that we are reaching the resolution limits of the lithography techniques. To go beyond this problem, we use the Atomic Force Microscope (AFM) nanolithography. To all the advantages brought by this technique we add those of using a silicon-on-insulator (SOI) substrate. In this article we are showing an example of a nanostructure fabricated by this method. Transport measurements and simulations performed on the device are in good agreement. We demonstrate the potential of using AFM lithography fabricated devices for applications like multi-gate transistors. Keywords : AFM lithography, SOI, single electron devices 1 INTRODUCTION Scanning probe microscopy (SPM) is a reliable technique that allows imaging and modification of the surface structure of the materials down to nanometric scales. The main advantage of SPM tools is the use of near-field interactions that allow a precise positioning of the probe (tip) next to the surface of the sample, which implies atomic resolution in the vertical plane. Other advantages of AFM techniques are its compatibility with the actual CMOS technologies and the fact that there are no proximity effects like in the e-beam technique. The probe can induce different kind of changes in the surface, for example the local oxidation of the surface of the sample by application of a voltage on the tip. The feasibility demonstration was made in 1990 by using another SPM technique, the Scanning Tunneling Microscopy (STM) oxidation on a Silicon surface [1]. Different ways of improving the technique were proposed : oxidation in tapping mode [2], the use of a pulsed tension on the tip [3]. We have chosen to use the oxidation by AFM in contact mode. Another advantage of our technique is the use of silicon-on-insulator (SOI) substrates. They ensure very thin monocrystalline top Si films with high quality interfaces, that are very important if we want to validate a reproducible process to fabricate the nanostructures. Using the AFM induced local oxidation on a SOI substrate, we have obtained silicon nanowires with lateral gates.